1. Technical Field
The present invention relates to a semiconductor device provided with a process monitor circuit in order to monitor fluctuation in circuit element characteristic due to any process change or variation and debug a result thereof, and a test method thereof.
2. Background Art
Generally, in manufacturing process of a semiconductor device, any fluctuation in characteristic is generated in any circuit element such as transistor that is an essential element of the semiconductor device or a logic gate formed in combination of the transistors due to variation in process conditions.
To overcome this, design is usually carried out taking such a fluctuation in characteristic of the circuit element due to variation in process into account (the fluctuation is hereinafter referred to as “fluctuation in process” or “process fluctuation”). However, in the case of any large variation in process conditions, there is a possibility that the characteristic of the circuit element fluctuates exceeding a value estimated preliminarily at the stage of designing. In such a case, with no way for any debug, there has been no alternative but to scrap it as a defective item.
Moreover, since it is necessary to consider the fluctuation in element characteristic due to the process variation whenever designing the semiconductor device, restriction such as timing control to secure an operation margin of the circuit element becomes large resulting in a restriction on the freedom in design.
In one of the prior arts, to monitor the fluctuation in element characteristic due to the process variation caused at the time of manufacturing a semiconductor device, a technique was proposed. In this technique, a test evaluation gate (TEG) is mounted on the same chip together with various circuit blocks performing required functions such that so-called built-in-test can be implemented. (For example, see the Japanese Patent Publications (unexamined) No. 12639/2000, the Japanese Patent Publications (unexamined) No. 127186/1997, etc.)
However, the mentioned conventional technique only makes it possible to monitor what level of fluctuation in element characteristic of the semiconductor device is generated due to the variation in process conditions, and never makes it possible to automatically debug the semiconductor device itself in which the fluctuation in process actually occurs.
That is, a result of monitor evaluated by means of the test evaluation gate is outputted to outside to early discover any defect, which is nothing but a suggestion for improvement in the process conditions of the semiconductor device. En effect, once fluctuation in process is generated, it is impossible to debug the element characteristic of the semiconductor device, individually for each element.
Therefore, when any element characteristic fluctuates exceeding a value estimated at the designing stage, there has been no choice but scrapping the semiconductor device as a defective item. Moreover, since it is necessary to consider the fluctuation in element characteristic due to the process variation whenever designing the semiconductor device, a large restriction on the operation timing becomes large. Consequently a problem exists in that freedom in the design is still limited.
In addition, several improvements in practical use such as in control method were proposed in the process monitor circuit for monitoring the fluctuation in element characteristic due to process variation disclosed in the foregoing prior arts. (See the Japanese Patent Publication (unexamined) No. 12639/2000, the Japanese Patent Publication (unexamined) No. 127186/1997, etc.) That is, in order to apply such known circuit to the semiconductor device, it is required to increase number of terminals, and because control of the process monitor circuit is not always simple, a further problem exits in that manufacturing cost of the semiconductor device is raised.